1. Technical Field
The present invention relates to a test apparatus for testing a device under test and a transmission apparatus.
2. Related Art
A test apparatus for testing a device under test (DUT) such as a semiconductor is known. The test apparatus uses a driver to generate a test signal and supply the generated test signal to the DUT. The test apparatus also receives a response signal output from the DUT in response to the supplied test signal and uses a comparator to detect the logic value of the received response signal. Based on the result of the detection, the test apparatus judges whether the DUT is acceptable. Here, a known test apparatus uses a single transmission line to transmit a test signal to one of the terminals of the DUT and to receive a response signal output from the one terminal (i.e., a single transmission connection test apparatus).
Referring to such a test apparatus, it is desired to generate the test signals at a shorter interval in order to reduce the overall test time. When the test apparatus generates the test signals at an interval shorter than the sum of double the transmission time through the transmission line and the response time of the DUT, however, the reception by the comparator of the response signal output from the DUT substantially concurrently occurs with the output of the next test signal from the driver. Which is to say, when the single transmission connection test apparatus is configured to generate the test signals at a too short interval, the response signal to be received by the comparator is superimposed by the next test signal output from the driver. As a result, the test apparatus cannot accurately detect the level of the response signal.
Patent Document 1 discloses a single transmission connection test apparatus that is capable of solving the above-described drawback. According to the disclosure of Patent Document 1, the test apparatus includes a driver that generates a voltage in accordance with a test signal, a replica driver that generates a voltage equal to the sum of the output voltage of the driver and a threshold voltage used for determining a logic level, a voltage divider circuit that resistance divides the output voltage of the replica driver based on the output resistance ratio between the driver and a DUT, and a comparator that detects the logic level of a response signal. According to the test apparatus, the comparator compares the response signal from the DUT with the divided voltage obtained as a result of the division by the voltage divider circuit, to detect the logic level of the response signal. With such a configuration, even when the reception of the response signal concurrently occurs with the output of the next test signal, the test apparatus disclosed in Patent Document 1 can accurately compare the response signal from the DUT with the threshold voltage by canceling the output voltage of the driver.
Patent Document 1: Japanese Patent Application Publication No. 2006-23233
Here, each DUT has a significantly different output resistance from other DUTs. In one example, each DUT is different by approximately 20% in terms of its output resistance than other DUTs. This makes it difficult for the test apparatus disclosed in Patent Document 1 to control the output resistance ratio between the driver and the DUT to be equal to the voltage dividing ratio of the voltage divider circuit. For this reason, the test apparatus disclosed in Patent Document 1 has difficulties in accurately canceling the output voltage of the driver for each DUT.
Furthermore, DUTs of a particular type may have a significantly different output resistance specification from DUTs of other types. If such is the case, the test apparatus disclosed in Patent Document 1 also cannot accurately cancel the output voltage of the driver for DUTs having a different output resistance specification.